module RegisterFile (Clock, A1, A2, A3, WD3, WE3, RD1, RD2);

	input					Clock;
	input					WE3;
	input		[4:0]		A1, A2, A3;
	input		[31:0]	WD3;
	output	[31:0]	RD1, RD2;
	
	reg		[31:0]	Regs		[31:0];
	
	always @(posedge Clock)
		if (WE3) Regs[A3] <= WD3;
	
	assign RD1 = Regs[A1];
	assign RD2 = Regs[A2];
endmodule
